A finite state machine (FSM) is implemented using the D flip-flops A and B, and logic gates, as shown in the figure below. The four possible states of the FSM are Q_AQ_B =00,01,10 and 11.

Assume that X_1N is is held at a constant logic level throughout the operation of the FSM. When the FSM is initialized to the state Q_AQ_B=00 and clocked, after a few clock cycles, it starts cycling through