A standard CMOS inverter is designed with equal rise and fal

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A standard CMOS inverter is designed with equal rise and fall times (β_n = β_p). If the width of the pMOS transistor in the inverter is increased, what would be the effect on the LOW noise margin (NM_L) and the HIGH noise margin NM_H?

[GATE EC 2019]

A

B

C

D No change in the noise margins.